repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.behavioral.pp.v | 2,623 | module MODULE1( VAR2, VAR8, VAR6, VAR5, VAR7, VAR4 );
input VAR8, VAR2, VAR6;
inout VAR7, VAR4;
output VAR5;
VAR9 VAR3(.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4));
VAR9 VAR1(.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR4(VAR4)); | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/udp_rx_joint_cmd.v | 1,522 | module MODULE1
(input VAR32,
input [7:0] VAR3,
input VAR18,
output [7:0] VAR31,
output [31:0] VAR9,
output [31:0] VAR19,
output [31:0] VAR14,
output [31:0] VAR10,
output VAR30);
wire [7:0] VAR16;
d1 #(8) VAR8(.VAR32(VAR32), .VAR22(VAR3), .VAR5(VAR16));
wire VAR23;
d1 VAR11(.VAR32(VAR32), .VAR22(VAR18), .VAR5(VAR23));
w... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/top/B100/B100.v | 8,880 | module MODULE1
(input VAR17, input VAR31, output [2:0] VAR133, output [31:0] VAR89, output [1:0] VAR62,
inout [15:0] VAR137, input [3:0] VAR42, output VAR51,
output [1:0] VAR11, output VAR102, output VAR124, output VAR96,
input VAR40,
inout VAR108, inout VAR82,
output VAR46, output VAR139, output VAR73, input VAR91, ou... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi_lp.v | 2,340 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR6,
VAR10,
VAR2,
VAR1 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR6;
input VAR10;
input VAR2;
input VAR1 ;
input VAR7 ;
VAR9 VAR8 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE2 ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/KOA.v | 5,871 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR3,
input wire [VAR15-1:0] VAR28,
input wire [VAR15-1:0] VAR27,
output wire [2*VAR15-1:0] VAR17
);
wire [1:0] VAR10;
wire [3:0] VAR38;
assign VAR10 = 2'b00;
assign VAR38 = 4'b0000;
wire [VAR15/2-1:0] VAR22;
wire [VAR15/2:0] VAR26;
wire [VAR15/2-3:0] VAR16;
w... | gpl-3.0 |
Anirudh94/Connect4-FPGA | Connect4/redDiskWin_bb.v | 4,924 | module MODULE1 (
address,
VAR2,
VAR1);
input [7:0] address;
input VAR2;
output [2:0] VAR1;
tri1 VAR2;
endmodule | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_rx_fifo.v | 10,835 | module MODULE1 # (
parameter VAR79 = 128,
parameter VAR5 = 64,
parameter VAR56 = 9
)
(
input VAR31,
input VAR40,
input VAR6,
input [VAR56-1:0] VAR73,
input [VAR79-1:0] VAR78,
input [VAR56:0] VAR36,
input [VAR56:0] VAR20,
input [9:4] VAR64,
output VAR26,
input VAR13,
input VAR42,
input VAR19,
output [VAR5-1:0] VAR76,
in... | gpl-3.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/i2c_master.v | 20,343 | module MODULE1(
clk, VAR7, reset,
VAR25, VAR31,
VAR35, VAR40,
VAR29, VAR3, VAR14, VAR43,
VAR17, VAR11,
VAR24 );
input clk;
input VAR7;
input reset;
inout VAR25, VAR31;
input [VAR26-1:0] VAR35;
output reg [VAR26-1:0] VAR40;
input VAR29;
input VAR3;
input VAR14;
input VAR43;
input VAR17;
output reg VAR11;
output reg [VAR... | gpl-2.0 |
egyp7/mor1kx | rtl/verilog/mor1kx_ctrl_espresso.v | 53,496 | module MODULE1
(
VAR88, VAR275, VAR183, VAR185, VAR7,
VAR272, VAR165, VAR128, VAR21,
VAR92, VAR115, VAR101,
VAR222, VAR60, VAR10, VAR30, VAR112,
VAR109, VAR266, VAR146, VAR168,
VAR256, VAR4, VAR17, VAR195,
VAR61, VAR225,
clk, rst, VAR103, VAR253, VAR34,
VAR214, VAR2, VAR228, VAR254,
VAR271, VAR190, VAR176,
VAR196, VAR2... | mpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/vfabric_branch_select.v | 4,391 | module MODULE1(VAR24, VAR32,
VAR12, VAR23, VAR27,
VAR36, VAR20, VAR18,
VAR39, VAR26, VAR11,
VAR28,
VAR3);
parameter VAR5 = 1;
parameter VAR6= 7;
parameter VAR22 = 64;
parameter VAR38 = 10;
input VAR24, VAR32;
input [VAR5-1:0] VAR12;
input [VAR5-1:0] VAR36;
input VAR23, VAR20;
output VAR27, VAR18;
output [VAR5-1:0] VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb4to1/sky130_fd_sc_hdll__muxb4to1.behavioral.pp.v | 3,155 | module MODULE1 (
VAR21 ,
VAR12 ,
VAR11 ,
VAR23,
VAR4,
VAR10 ,
VAR14
);
output VAR21 ;
input [3:0] VAR12 ;
input [3:0] VAR11 ;
input VAR23;
input VAR4;
input VAR10 ;
input VAR14 ;
wire VAR25;
wire VAR5;
wire VAR6;
wire VAR1;
wire VAR9;
wire VAR22;
wire VAR13;
wire VAR16;
VAR3 VAR8 (VAR25, VAR12[0], VAR23, VAR4 );
VAR3 V... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/CPC2_DE10.v | 8,688 | module MODULE1(
input VAR15,
input VAR92,
input VAR110,
inout VAR130,
inout VAR64,
inout VAR76,
inout VAR117,
inout VAR88,
inout VAR107,
output VAR62,
output VAR78,
output [23:0] VAR35,
output VAR1,
input VAR102,
output VAR56,
input [1:0] VAR86,
output [7:0] VAR89,
input [3:0] VAR65,
inout [35:0] VAR120,
inout [35:0] V... | gpl-3.0 |
pdaxrom/p601zero | pagesel.v | 1,188 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR7,
input wire [7:0] VAR9,
output reg [7:0] VAR1,
input wire VAR6,
input wire VAR5,
output reg [3:0] VAR10,
output reg VAR3,
output reg VAR8,
output reg VAR4,
output reg VAR2
);
always @ (posedge clk) begin
if (rst) begin
VAR10 <= 4'b0000;
VAR3 <= 0;
VAR8 <=... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp_lp.v | 2,138 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3 ,
VAR7,
VAR5,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR7;
input VAR5;
input VAR4 ;
input VAR8 ;
VAR9 VAR1 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2 ,
VAR6 ,
VAR3
);
output VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.functional.v | 1,071 | module MODULE1 ();
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_video_decoder_0.v | 6,565 | module MODULE1 (
clk,
reset,
VAR31,
VAR36,
VAR15,
VAR5,
VAR18,
VAR3,
VAR22,
VAR6,
VAR41,
VAR26,
VAR1,
VAR8,
VAR35
);
parameter VAR38 = 7;
parameter VAR28 = 15;
parameter VAR10 = 17;
parameter VAR19 = 1280;
input clk;
input reset;
input VAR31;
input [ 7: 0] VAR36;
input VAR15;
input VAR5;
input VAR18;
input VAR3;
output... | gpl-3.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_mm_interconnect_2.v | 16,977 | module MODULE1 (
input wire VAR3, input wire VAR74, input wire VAR53, input wire VAR89, input wire [29:0] VAR72, output wire VAR80, input wire [0:0] VAR94, input wire [7:0] VAR57, input wire VAR4, output wire [63:0] VAR33, output wire VAR13, input wire VAR22, input wire [63:0] VAR10, input wire VAR96, output wire [3:0]... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.behavioral.pp.v | 3,372 | module MODULE1( VAR11, VAR6, VAR7, VAR5, VAR3, VAR10, VAR2, VAR8 );
input VAR10, VAR3, VAR6, VAR11, VAR7;
inout VAR2, VAR8;
output VAR5;
VAR4 VAR1(.VAR11(VAR11),.VAR6(VAR6),.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3),.VAR10(VAR10),.VAR2(VAR2),.VAR8(VAR8));
VAR4 VAR9(.VAR11(VAR11),.VAR6(VAR6),.VAR7(VAR7),.VAR5(VAR5),.VAR3(VAR3)... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_iqcor.v | 4,537 | module MODULE1 (
clk,
valid,
VAR26,
VAR19,
VAR13,
VAR21,
VAR9,
VAR16,
VAR8);
parameter VAR12 = 0;
input clk;
input valid;
input [15:0] VAR26;
input [15:0] VAR19;
output VAR13;
output [15:0] VAR21;
input VAR9;
input [15:0] VAR16;
input [15:0] VAR8;
reg VAR15 = 'd0;
reg [15:0] VAR20 = 'd0;
reg [15:0] VAR22 = 'd0;
reg [33... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bwjx1c64a/ExShad64.v | 8,066 | module MODULE1(
VAR5, reset,
VAR46, VAR110,
VAR35, VAR71
);
input VAR5;
input reset;
input[63:0] VAR46;
input[ 7:0] VAR110;
input[ 2:0] VAR71;
output[63:0] VAR35;
reg[63:0] VAR4;
assign VAR35 = VAR4;
reg[63:0] VAR108;
reg[63:0] VAR50;
reg[ 7:0] VAR38;
always @*
begin
VAR108=0;
VAR50=0;
VAR4 = 0;
VAR38 = 0;
case(VAR71)
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2.symbol.v | 1,330 | module MODULE1 (
input VAR2,
input VAR5,
output VAR7 ,
input VAR3
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.pp.symbol.v | 1,448 | module MODULE1 (
input VAR1,
input VAR7,
input VAR2 ,
input VAR6 ,
output VAR5 ,
input VAR9 ,
input VAR8,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.behavioral.pp.v | 1,172 | module MODULE1( VAR5, VAR2, VAR1, VAR7 );
input VAR5;
inout VAR1, VAR7;
output VAR2;
VAR6 VAR4(.VAR5(VAR5),.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7));
VAR6 VAR3(.VAR5(VAR5),.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7)); | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_int_div64u.v | 4,809 | module MODULE1 (
enable,
VAR8,
VAR22,
VAR23,
VAR10,
VAR17);
input enable;
input VAR8;
input [63:0] VAR22;
input [63:0] VAR23;
output [63:0] VAR10;
output [63:0] VAR17;
wire [63:0] VAR13;
wire [63:0] VAR15;
wire [63:0] VAR17 = VAR13[63:0];
wire [63:0] VAR10 = VAR15[63:0];
VAR2 VAR6 (
.VAR8 (VAR8),
.VAR9 (enable),
.VAR22... | mit |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/SendChars.v | 1,594 | module MODULE1(VAR4, VAR7, VAR6, VAR5, VAR8, VAR3, VAR10, VAR11, VAR2);
input [5:0] VAR4;
input VAR7, VAR6, VAR5, VAR8, VAR3;
output reg [5:0] VAR10;
output reg VAR11, VAR2;
reg [1:0] VAR1;
parameter [5:0] VAR12 = 6'd32;
parameter [5:0] VAR9 = 6'd33;
always @ (posedge VAR7)
if (VAR6 == 1) begin VAR2 <= 1'b0; VAR10 <= 6... | mit |
peteasa/oh | src/spi/hdl/spi.v | 5,282 | module MODULE1 #( parameter VAR24 = 32, parameter VAR9 = 104, parameter VAR25 = 13 )
( input VAR17, input clk, input VAR21, output VAR27, input VAR3, input [VAR9-1:0] VAR13, input VAR4, output VAR14, output [VAR9-1:0] VAR15, output VAR31, output VAR7, output VAR20, output VAR11, input VAR30, input VAR10, input VAR35, i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.v | 2,163 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR3,
VAR7,
VAR2 ,
VAR1
);
output VAR6 ;
input VAR8 ;
input VAR3;
input VAR7;
input VAR2 ;
input VAR1 ;
VAR5 VAR4 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR6,
VAR8
);
output VAR6;
input VAR8;
supply1 VAR3;
supply0 VAR7;... | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/mem_wb.v | 3,342 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR14,
input wire[4:0] VAR30,
input wire[31:0] VAR5,
input wire[31:0] VAR34,
input wire[31:0] VAR8,
input wire VAR21,
input wire VAR35,
input wire[4:0] VAR12,
input wire VAR29,
input wire[3:0] VAR33,
input wire[31:0] VAR26,
input wire[31:0] VAR38,
input wire VA... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.pp.symbol.v | 1,408 | module MODULE1 (
input VAR1 ,
input VAR7 ,
input VAR8 ,
input VAR3 ,
input VAR2 ,
output VAR10 ,
input VAR6 ,
input VAR4,
input VAR9,
input VAR5
);
endmodule | apache-2.0 |
amrmorsey/Digital-Design-Project | clockdivide2.v | 1,222 | module MODULE1(
input clk,
input rst,
input select,
output reg [31:0] VAR2,
output reg [31:0] VAR4,
output VAR3,
output VAR1,
output VAR5
);
always @ (posedge clk or posedge rst)
begin
if (rst)
VAR2<=32'd0;
end
else
if (VAR2 == 32'd50000000)
VAR2<=32'd0;
else
VAR2 <= VAR2 + 1;
end
always @ (posedge clk or posedge rst)
... | gpl-2.0 |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_member_ctrl.tsmc90.v | 9,481 | module MODULE1 (
input VAR78,
input VAR25,
input VAR117,
input VAR128,
input VAR24,
output VAR101,
output VAR63,
input VAR27,
input VAR11,
output VAR29,
output VAR15,
output VAR20,
output VAR39,
output VAR104,
output VAR106,
input VAR49,
output VAR38,
input VAR58,
input VAR23,
input [3:0] VAR21,
output [3:0] VAR37,
out... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_SLVT_TT_210930.v | 231,331 | module MODULE1 (VAR3, VAR5, VAR9, VAR6, VAR11);
output VAR3;
input VAR5, VAR9, VAR6, VAR11;
wire VAR8, VAR4, VAR10;
wire VAR7, VAR2, VAR1;
not (VAR7, VAR11);
not (VAR10, VAR6);
not (VAR4, VAR9);
and (VAR2, VAR4, VAR10);
not (VAR8, VAR5);
and (VAR1, VAR8, VAR10);
or (VAR3, VAR1, VAR2, VAR7); | bsd-3-clause |
olajep/oh | src/common/hdl/oh_fifo_async.v | 3,162 | module MODULE1 # (parameter VAR1 = 104, parameter VAR15 = 32, parameter VAR3 = "VAR24", parameter VAR28 = (VAR15/2), parameter VAR22 = VAR16(VAR15) )
(
input VAR8, input VAR17, input VAR20, input [VAR1-1:0] din, input VAR26, input VAR23, output [VAR1-1:0] dout, output VAR9, output VAR25, output VAR5, output [VAR22-1:0]... | mit |
eda-globetrotter/PicenoDecoders | viterbi/syn/src/spd.v | 5,473 | module MODULE1 (VAR85, VAR21, VAR50, VAR88, VAR22, VAR87, VAR8, VAR57, out, clk, reset);
output out;
input VAR85, VAR21, VAR50, VAR88;
input [3:0] VAR22, VAR87, VAR8, VAR57;
input clk, reset;
wire out;
wire VAR77, VAR24;
wire VAR58, VAR49, VAR81, VAR18;
wire VAR59, VAR27, VAR70, VAR80;
wire VAR30, VAR64, VAR45, VAR62;
... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_sct_out_queues.v | 15,202 | module MODULE1 (
VAR2, VAR77, VAR94,
VAR142, VAR19, VAR8, VAR147,
VAR129,
VAR83, VAR65, VAR84,
VAR89, VAR150, VAR88, VAR73, VAR110, VAR18, VAR123,
clk, VAR66, VAR96, VAR105
);
input [31:0] VAR83;
input VAR65; input VAR84;
output [3:0] VAR2;
output VAR77;
output VAR94;
output VAR142;
output [5:0] VAR19;
output [127:0] V... | gpl-2.0 |
Fairyland0902/BlockyRoads | src/BlockyRoads/Renderer.v | 142,193 | module MODULE1(
input wire clk, VAR37,
input wire [ 3: 0] VAR20,
input wire VAR4,
input wire [ 9: 0] VAR75, VAR28,
input wire VAR63, VAR31, VAR64, VAR68, VAR67,
input wire VAR14, VAR82,
input wire VAR87, VAR33, VAR65, VAR78, VAR22,
input wire VAR11, VAR56, VAR38, VAR97,
input wire VAR47, VAR69, VAR71, VAR9, VAR90,
inpu... | mit |
gigglesninja/digital-system-design | Lab6bonus - Copy/ledtimer.v | 2,784 | module MODULE1(
output [7:0] VAR14,
input [1:0] VAR13,
input VAR15
);
wire clk, reset, VAR9, VAR5, VAR2;
wire [1:0] addr;
wire [31:0] VAR26, VAR16, VAR11, VAR23, VAR22, VAR6, VAR27, VAR4, din;
assign addr = 2'b10;
assign VAR9 = 0;
assign VAR5 = 1;
assign clk = VAR15;
assign VAR14[0] = VAR26[2];
assign VAR14[1] = VAR16[... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxtp/sky130_fd_sc_hvl__dfxtp.symbol.v | 1,318 | module MODULE1 (
input VAR2 ,
output VAR7 ,
input VAR3
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/output_queues.v | 14,400 | module MODULE1
parameter VAR47 = 64,
parameter VAR104=VAR47/8,
parameter VAR111 = 2,
parameter VAR64 = 4,
parameter VAR118 = 8,
parameter VAR44 = 6,
parameter VAR23 = 13
)
( VAR82,
VAR71,
VAR57,
VAR72,
VAR21,
VAR69,
VAR19,
VAR70,
VAR79,
VAR73,
VAR76,
VAR32,
VAR68,
VAR84,
VAR89,
VAR77,
VAR48,
VAR61,
VAR109,
VAR10,
VAR90... | mit |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_mc_we.v | 2,751 | module MODULE1
(
input VAR3, input VAR1,
input VAR5, input VAR6,
output reg VAR7, output reg VAR4 );
reg VAR2;
always @(posedge VAR3, negedge VAR1) begin
if(!VAR1) VAR2 <= 1'b0;
end
else begin
case(VAR2)
1'b0: if(VAR5) VAR2 <= 1'b1;
end
else VAR2 = 1'b0;
1'b1: if(VAR5) VAR2 <= 1'b0;
else VAR2 = 1'b1;
endcase
end
end
al... | gpl-3.0 |
gigglesninja/digital-system-design | uart/baudgen.v | 1,276 | module MODULE1(VAR1, VAR5, reset, din, clk, VAR6, VAR4, dout);
input VAR1, VAR5, reset, clk, VAR6;
input [7:0] din;
output VAR4;
output [7:0] dout;
parameter VAR2 = 8'h0F;
reg [7:0] VAR3, period, dout;
reg VAR4;
always @(posedge clk or posedge reset) begin
if(reset)
VAR3 <= 8'h00;
end
else begin
VAR3 <= VAR3 + 1;
if(VA... | gpl-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_pll_pwm.v | 2,080 | module MODULE1(
input wire VAR53,
input wire rst,
output wire VAR65,
output wire VAR52
);
VAR24 #(
.VAR69("false"),
.VAR38("25.0 VAR20"),
.VAR17("VAR46"),
.VAR15(1),
.VAR70("125.500000 VAR20"),
.VAR61("0 VAR23"),
.VAR13(50),
.VAR27("0 VAR20"),
.VAR66("0 VAR23"),
.VAR29(50),
.VAR3("0 VAR20"),
.VAR34("0 VAR23"),
.VAR6(50... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/wb_intercon.v | 18,246 | module MODULE1
(input VAR125,
input VAR2,
input [31:0] VAR148,
input [31:0] VAR170,
input [3:0] VAR166,
input VAR46,
input VAR115,
input VAR184,
input [2:0] VAR95,
input [1:0] VAR121,
output [31:0] VAR20,
output VAR211,
output VAR74,
output VAR178,
input [31:0] VAR9,
input [31:0] VAR78,
input [3:0] VAR75,
input VAR35,
... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/master_clock.v | 17,369 | module MODULE1 (
input wire VAR5, input wire rst, output wire VAR3, output wire VAR1 );
VAR6 VAR2 (
.VAR5 (VAR5), .rst (rst), .VAR3 (VAR3), .VAR1 (VAR1), .VAR4 () );
endmodule | gpl-3.0 |
mbus/mbus | layer_controller_v1/verilog/layer_ctrl_r4494.v | 19,342 | module MODULE1(
VAR97,
VAR73,
VAR39,
VAR38,
VAR83,
VAR82,
VAR48,
VAR71,
VAR65,
VAR25,
VAR95,
VAR1,
VAR43,
VAR100,
VAR37,
VAR98,
VAR22,
VAR60,
VAR41,
VAR76,
VAR3,
VAR13,
VAR50,
VAR47,
VAR80,
VAR102,
VAR19,
VAR87,
VAR67,
VAR11,
VAR53,
VAR106
);
parameter VAR12 =24;
parameter VAR27 =VAR31-VAR12;
parameter VAR69 = 128;
par... | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T28-ram/genram.v | 1,808 | module MODULE1 #( parameter VAR7 = 5, parameter VAR3 = 4)
( input clk, input wire [VAR7-1: 0] addr, input wire VAR10, input wire [VAR3-1: 0] VAR9, output reg [VAR3-1: 0] VAR1);
parameter VAR6 = "VAR8.VAR2";
localparam VAR4 = 2 ** VAR7;
reg [VAR3-1: 0] VAR5 [0: VAR4-1];
always @(posedge clk) begin
if (VAR10 == 1)
VAR1 <... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi.behavioral.v | 1,722 | module MODULE1 (
VAR13 ,
VAR2,
VAR7,
VAR9 ,
VAR14
);
output VAR13 ;
input VAR2;
input VAR7;
input VAR9 ;
input VAR14 ;
supply1 VAR5;
supply0 VAR15;
supply1 VAR8 ;
supply0 VAR3 ;
wire VAR16 ;
wire VAR6 ;
wire VAR11;
and VAR1 (VAR16 , VAR9, VAR14 );
nor VAR4 (VAR6 , VAR2, VAR7 );
nor VAR10 (VAR11, VAR6, VAR16);
buf VAR12... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/PIO_TO_CTRL.v | 3,929 | module MODULE1 (
clk,
VAR6,
VAR5,
VAR4,
VAR1,
VAR3
);
input clk;
input VAR6;
input VAR5;
input VAR4;
input VAR1;
output VAR3;
reg VAR2;
reg VAR3;
always @ ( posedge clk or negedge VAR6 ) begin
if (!VAR6 ) begin
VAR2 <= 0;
end else begin
if (!VAR2 && VAR5)
VAR2 <= 1'b1;
end
else if (VAR4)
VAR2 <= 1'b0;
end
end
always @ ... | lgpl-3.0 |
jotego/jt12 | hdl/jt12_pcm.v | 2,829 | module MODULE1(
input rst,
input clk,
input VAR2 ,
input VAR9,
input signed [8:0] VAR22,
input VAR6,
output reg signed [8:0] VAR16
);
reg VAR4;
wire VAR14 = !VAR4 && VAR9;
reg VAR17, VAR1; reg VAR10, VAR21;
always @(posedge clk, posedge rst)
if(rst)
VAR1 <= 1'b0;
else begin
VAR4 <= VAR9;
VAR17 <= VAR14;
if(VAR14) begin... | gpl-3.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/clk_gen_top/clk_gated_module.v | 5,114 | module MODULE1(
VAR4 , VAR3 , VAR1 );
input VAR4 ; input VAR3 ; output VAR1 ;
reg VAR5 ;
always @(posedge VAR4) begin : VAR2
VAR5 <= VAR3;
end
assign VAR1 = VAR5 & VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver.behavioral.v | 1,372 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR1;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR3 ;
wire VAR8;
buf VAR6 (VAR8, VAR4 );
buf VAR2 (VAR5 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrbp/sky130_fd_sc_hd__dfrbp_2.v | 2,441 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR2 ,
VAR6 ,
VAR7,
VAR11 ,
VAR1 ,
VAR8 ,
VAR3
);
output VAR9 ;
output VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR7;
input VAR11 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
VAR10 VAR4 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.... | apache-2.0 |
jamesbowman/swapforth | j1a/icestorm/j1a.v | 11,132 | module MODULE4(
output [1:0] VAR162,
input VAR42, VAR163, VAR166,
input [10:0] VAR49,
input VAR150, VAR131, VAR147,
input [10:0] VAR107,
input [1:0] VAR157, VAR156
);
parameter VAR164 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR5 = 256'h00000000000000000000000000000000000000000... | bsd-3-clause |
osrf/wandrr | firmware/motor_controller/fpga/meganode_wrapper.v | 2,465 | module MODULE1
( input clk, output VAR57, output [3:0] VAR30,
output VAR55, output VAR40, output VAR69, inout VAR38,
output [1:0] VAR53, output [3:0] VAR63,
input [1:0] VAR73, input [3:0] VAR17,
output [4:0] VAR3, output [4:0] VAR33,
inout [4:0] VAR25, inout [4:0] VAR34,
output [2:0] VAR37, output [2:0] VAR16, output V... | apache-2.0 |
gtaylormb/fpga_nes | hw/src/cpu/rp2a03.v | 4,915 | module MODULE1
(
input wire VAR31, input wire VAR35,
input wire VAR50, input wire [ 7:0] din, input wire VAR37, input wire VAR5, output wire [ 7:0] dout, output wire [15:0] VAR23, output wire VAR52, output wire VAR28,
input wire VAR38, input wire VAR8, output wire VAR48, output wire VAR39,
input wire [ 3:0] VAR15, outp... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b_2.v | 2,311 | module MODULE2 (
VAR3 ,
VAR9 ,
VAR8 ,
VAR10 ,
VAR6 ,
VAR11,
VAR5,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR10 ;
input VAR6 ;
input VAR11;
input VAR5;
input VAR1 ;
input VAR2 ;
VAR7 VAR4 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR1(VAR1),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi_1.v | 2,350 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR10 ,
VAR6 ,
VAR5 ,
VAR3,
VAR4,
VAR1 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR10 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR8 ;
VAR11 VAR7 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4_1.v | 2,258 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR11 ,
VAR5 ,
VAR2 ,
VAR3,
VAR4,
VAR1 ,
VAR10
);
output VAR7 ;
input VAR8 ;
input VAR11 ;
input VAR5 ;
input VAR2 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR10 ;
VAR6 VAR9 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn_2.v | 2,204 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR9,
VAR6 ,
VAR5 ,
VAR7 ,
VAR3
);
output VAR8 ;
input VAR2 ;
input VAR9;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
VAR4 VAR1 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR8 ,
VAR2 ,
VAR9
);
output VA... | apache-2.0 |
cynngah/virtualsynthesizer | vga_pll.v | 8,650 | module MODULE1 (
VAR16,
VAR23);
input VAR16;
output VAR23;
wire [5:0] VAR2;
wire [1:0] VAR12;
wire VAR11;
assign VAR11 = 1'b0;
assign VAR12 = { VAR11, VAR16 };
VAR17 VAR10 (
.VAR7 (VAR12),
.clk (VAR2)
);
VAR10.VAR14 = "VAR3",
VAR10.VAR9 = "VAR13 VAR20",
VAR10.VAR25 = "VAR17",
VAR10.VAR24 = "VAR8",
VAR10.VAR19 = 20000,... | mit |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_async_frame_fifo_64.v | 7,192 | module MODULE1 #
(
parameter VAR43 = 12,
parameter VAR35 = 64,
parameter VAR29 = (VAR35/8),
parameter VAR20 = 0
)
(
input wire VAR39,
input wire VAR42,
input wire [VAR35-1:0] VAR18,
input wire [VAR29-1:0] VAR1,
input wire VAR3,
output wire VAR30,
input wire VAR11,
input wire VAR21,
input wire VAR28,
input wire VAR17,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.behavioral.pp.v | 2,084 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR3,
VAR8 ,
VAR6 ,
VAR12
);
output VAR10 ;
input VAR1 ;
input VAR3;
input VAR8 ;
input VAR6 ;
input VAR12 ;
wire VAR11;
wire VAR9 ;
VAR7 VAR5 (VAR11, VAR1, VAR3, VAR6 );
buf VAR2 (VAR9 , VAR11 );
VAR7 VAR4 (VAR10 , VAR9, VAR8, VAR6);
endmodule | apache-2.0 |
SymbiFlow/yosys | techlibs/intel/cycloneive/cells_map.v | 3,435 | module \VAR10 (input VAR3, output VAR20);
VAR18 VAR7 (.VAR13(VAR20), .VAR9(VAR3), .VAR19(1'b0));
endmodule
module \VAR22 (input VAR3, output VAR20);
VAR8 VAR7 (.VAR13(VAR20), .VAR9(VAR3), .VAR23(1'b1));
endmodule
module MODULE1 (VAR5, VAR11);
parameter VAR2 = 0;
parameter VAR4 = 0;
input [VAR2-1:0] VAR5;
output VAR11;
... | isc |
HSID/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/read_req_wrapper.v | 5,781 | module MODULE1(
input clk,
input rst,
input VAR5, input [4:0] VAR25,
input [31:0] VAR1,
input VAR30,
input [4:0] VAR15,
input [31:0] VAR26,
input VAR4,
input [4:0] VAR23,
output [31:0] VAR21,
input VAR16, output [31:0] VAR17,
output VAR13
);
reg VAR8;
reg [4:0] VAR12;
reg [31:0] VAR9;
reg [4:0] VAR20;
wire [4:0] VAR18;... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_3.behavioral.v | 1,108 | module MODULE1( VAR2, VAR5 );
input VAR2;
output VAR5;
VAR1 VAR3(.VAR2(VAR2),.VAR5(VAR5));
VAR1 VAR4(.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o.functional.v | 1,471 | module MODULE1 (
VAR2 ,
VAR7,
VAR3,
VAR4,
VAR11,
VAR8
);
output VAR2 ;
input VAR7;
input VAR3;
input VAR4;
input VAR11;
input VAR8;
wire VAR5 ;
wire VAR10;
and VAR1 (VAR5 , VAR4, VAR7, VAR3 );
or VAR9 (VAR10, VAR5, VAR8, VAR11);
buf VAR6 (VAR2 , VAR10 );
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/wb_intercon-1.0/rtl/verilog/wb_upsizer.v | 5,692 | module MODULE1
parameter VAR12 = 0,
parameter VAR18 = 32)
(input VAR31,
input VAR39,
input [VAR18-1:0] VAR17,
input [VAR37-1:0] VAR20,
input [VAR37/8-1:0] VAR3,
input VAR59,
input VAR2,
input VAR61,
input [2:0] VAR58,
input [1:0] VAR5,
output [VAR37-1:0] VAR35,
output VAR8,
output VAR36,
output VAR19,
output [VAR18-1:0... | mit |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_sysid_qsys_0.v | 1,456 | module MODULE1 (
address,
VAR3,
VAR2,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR3;
input VAR2;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1411627075 : 0;
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ethmac/eth_rxcounters.v | 6,983 | module MODULE1
(
VAR12, VAR36, VAR2, VAR28, VAR11, VAR35, VAR18, VAR29,
VAR9, VAR32, VAR16, VAR7, VAR8, VAR24, VAR19, VAR1,
VAR22, VAR25, VAR30,VAR34,VAR10,VAR17, VAR6,
VAR33, VAR15, VAR3, VAR14, VAR23
);
input VAR12;
input VAR36;
input VAR2;
input VAR11;
input [1:0] VAR35;
input VAR9;
input VAR28;
input VAR18;
input V... | mit |
jayant-sharma/ft2232h-fifo | hdl/dp_sync_fifo.v | 1,916 | module MODULE1 #(
parameter VAR3 = 64,
parameter VAR16 = 1024,
parameter VAR13 = VAR12(VAR16)
)(
input rst,
input clk,
input VAR7,
input VAR4,
input [VAR3-1:0] VAR9,
output [VAR3-1:0] VAR8,
input VAR15,
input VAR14,
input [VAR3-1:0] VAR20,
output [VAR3-1:0] VAR19,
output VAR17,
output VAR10,
output VAR5
);
reg [VAR13:0... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.functional.v | 1,364 | module MODULE1 (
VAR3 ,
VAR7,
VAR8
);
output VAR3 ;
input VAR7;
input VAR8 ;
wire VAR6 ;
wire VAR5;
not VAR1 (VAR6 , VAR8 );
or VAR2 (VAR5, VAR6, VAR7 );
buf VAR4 (VAR3 , VAR5 );
endmodule | apache-2.0 |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v | 25,585 | module MODULE1 #(
parameter VAR198 = 0,
parameter integer VAR8 = 4,
parameter integer VAR42 = 30,
parameter integer VAR52 = 32,
parameter integer VAR26 = 1,
parameter integer VAR134 = 1
)
(
input wire VAR99 ,
input wire VAR152 ,
input wire [VAR8-1:0] VAR196 ,
input wire [VAR42-1:0] VAR11 ,
input wire [((VAR198 == 1) ? ... | mit |
cr88192/bgbtech_bjx1core | srvcore/DecOp.v | 7,536 | module MODULE1(
clk,
VAR8,
VAR4,
VAR1,
VAR12,
VAR3,
VAR13,
VAR10,
VAR11,
VAR7
);
input clk; input[31:0] VAR8; input[31:0] VAR4;
output[6:0] VAR1;
output[6:0] VAR12;
output[6:0] VAR3;
output[31:0] VAR13;
output[1:0] VAR10;
output[11:0] VAR11;
output[31:0] VAR7;
reg[11:0] VAR5[256];
reg[31:0] VAR9[4096];
reg[7:0] VAR6;
r... | mit |
secworks/uart | src/rtl/uart.v | 8,663 | module MODULE1(
input wire clk,
input wire VAR45,
input wire VAR27,
input wire VAR22,
input wire [7 : 0] address,
input wire [31 : 0] VAR35,
output wire [31 : 0] VAR39,
input wire VAR20,
output wire VAR13
);
localparam VAR15 = 8'h00;
localparam VAR32 = 8'h01;
localparam VAR41 = 8'h02;
localparam VAR3 = 8'h10;
localpara... | bsd-2-clause |
rkrajnc/minimig-de1 | rtl/ctrl/ctrl_top.v | 14,433 | module MODULE1 (
input wire VAR21,
input wire VAR11,
output wire VAR30,
output wire VAR42,
output wire VAR14,
output wire VAR5,
input wire VAR32,
input wire [ 4-1:0] VAR41,
output wire VAR35,
output wire VAR39,
output wire VAR25,
output wire VAR44,
output wire [ 4-1:0] VAR24,
input wire [ 4-1:0] VAR19,
output wire [ 18... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2_6.v | 2,102 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR9 ,
VAR7,
VAR3,
VAR4 ,
VAR6
);
output VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR7;
input VAR3;
input VAR4 ;
input VAR6 ;
VAR2 VAR8 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR5,
VAR1,
VAR9
);
output VAR5;
... | apache-2.0 |
UA3MQJ/fpga-synth | modules/note2dds_1st_gen.v | 4,159 | module MODULE1(VAR3, VAR1, VAR2);
input wire VAR3;
input wire [6:0] VAR1;
output reg [31:0] VAR2; | gpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Voters/Output_Voter.v | 2,711 | module MODULE1(
input VAR32,
input [3:0] VAR27,
input [29:0] VAR19,
input [31:0] VAR33,
input [29:0] VAR34,
input VAR30,
input VAR12,
input [3:0] VAR10,
input [29:0] VAR36,
input [31:0] VAR7,
input [29:0] VAR20,
input VAR4,
input VAR21,
input [3:0] VAR26,
input [29:0] VAR18,
input [31:0] VAR14,
input [29:0] VAR13,
inpu... | lgpl-3.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v | 28,427 | module MODULE1 (
VAR184,
VAR138,
VAR17,
VAR55,
VAR97,
VAR64,
VAR225,
VAR189,
VAR45,
VAR85,
VAR66,
VAR155,
VAR133,
VAR49,
VAR183,
VAR177,
VAR25,
VAR11,
VAR136,
VAR103,
VAR158,
VAR91,
VAR71,
VAR194,
VAR157,
VAR144,
VAR46,
VAR1,
VAR48,
VAR134,
VAR96,
VAR154,
VAR213,
VAR12,
VAR173,
VAR34,
VAR118,
VAR68,
VAR182,
VAR26,
VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.behavioral.pp.v | 2,184 | module MODULE1 (
VAR10 ,
VAR15,
VAR17,
VAR19 ,
VAR2 ,
VAR4,
VAR14,
VAR18 ,
VAR5
);
output VAR10 ;
input VAR15;
input VAR17;
input VAR19 ;
input VAR2 ;
input VAR4;
input VAR14;
input VAR18 ;
input VAR5 ;
wire VAR3 ;
wire VAR16 ;
wire VAR8 ;
wire VAR9;
nand VAR6 (VAR3 , VAR17, VAR15 );
or VAR1 (VAR16 , VAR2, VAR19 );
nan... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/MódulosBásicos/ps2/ps2.v | 1,511 | module MODULE1 ( input VAR1,
input VAR4,
output reg VAR3,
output [7:0] VAR10,
output reg VAR8
);
reg [8:0] VAR9;
reg [7:0] VAR5;
reg [3:0] VAR7;
reg [3:0] VAR6;
reg VAR2;
begin
begin
begin
begin
begin
begin
begin
end
begin | gpl-3.0 |
foshardware/qtflow | tech/osu018/osu018_stdcells.v | 24,158 | module MODULE1 (VAR2, VAR1, VAR3);
input VAR2 ;
input VAR1 ;
output VAR3 ;
and (VAR3, VAR2, VAR1); | lgpl-3.0 |
Murailab-arch/magukara | boards/ecp3versa/rtl/ipexpress/ecp3/rcx1/pcie_eval/models/ecp3/sync1s.v | 3,721 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR2 ,
VAR3,
VAR10
);
parameter VAR1 = 1 ;
input VAR7 ; input VAR11 ; input VAR2 ; input [VAR1-1:0] VAR3 ; output [VAR1-1:0] VAR10 ;
reg [VAR1-1:0] VAR5 ;
reg [VAR1-1:0] VAR6 ;
reg [VAR1-1:0] VAR9 ;
reg [VAR1-1:0] VAR8 ;
reg [VAR1-1:0] VAR12 ;
wire [VAR1-1:0] VAR4 ;
wire [VAR1-1:0] VAR10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2_1.v | 1,948 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR5,
VAR7
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR7;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR4,
VAR1,
VAR3
);
output VAR4;
input VAR1;
input VAR3;
supply1 VAR5;
supply0 VAR7;
VAR2 VAR6 (
.... | apache-2.0 |
GLADICOS/AES128 | rtl/sBox.v | 2,369 | module MODULE1
parameter VAR4 = 4
)(
output [8*VAR4 - 1:0] VAR7,
output [8*VAR4 - 1:0] VAR5,
input [8*VAR4 - 1:0] VAR6,
input VAR2,
input clk
);
VAR3 VAR1[VAR4 - 1:0]
(
.VAR7 ( VAR7 ),
.VAR5 ( VAR5 ),
.VAR6 ( VAR6 ),
.VAR2 ( VAR2 ),
.clk ( clk )
);
endmodule | lgpl-3.0 |
Marcoslz22/Tercer_Proyecto | Contador_Control_de_Tiempos.v | 7,786 | module MODULE1(
input reset,
input clk,
input VAR4,
input VAR6,
input VAR9,
input VAR7,
input [2:0] VAR3,
output [3:0] VAR5
);
reg [5:0] VAR8 = 0;
reg [3:0] VAR1 = 0;
reg VAR2 = 0;
assign VAR5 = VAR1;
always @(posedge clk )
if (reset)
begin
VAR1 = 0;
VAR8 <= 0;
end
else
begin
begin
if ((VAR9 && VAR4) || VAR6 || (VAR3==... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21a/sky130_fd_sc_hd__o21a_1.v | 2,248 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR1,
VAR4,
VAR8 ,
VAR7
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR8 ;
input VAR7 ;
VAR5 VAR2 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
praveendath92/securePUF | source/sirc_files/iobuf.v | 1,214 | module MODULE1(VAR7, VAR8, VAR5, VAR1);
inout wire [15:0] VAR7;
input wire [15:0] VAR8;
output wire [15:0] VAR5;
input wire VAR1;
VAR6 VAR4(.VAR7(VAR7[0]), .VAR8(VAR8[0]), .VAR5(VAR5[0]), .VAR1(VAR1));
VAR6 VAR19(.VAR7(VAR7[1]), .VAR8(VAR8[1]), .VAR5(VAR5[1]), .VAR1(VAR1));
VAR6 VAR2(.VAR7(VAR7[2]), .VAR8(VAR8[2]), .VA... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/ppu.v | 18,709 | module MODULE1(
input clk,
input VAR101,
input reset,
input [63:0] VAR71,
input [15:0] VAR40,
input VAR136,
input VAR132,
output VAR107,
input [63:0] VAR28,
input [15:0] VAR38,
input VAR210,
input VAR18,
output VAR127,
input [63:0] VAR215,
input [15:0] VAR33,
input VAR66,
input VAR118,
output VAR65,
input [63:0] VAR182... | mit |
alexforencich/verilog-ethernet | rtl/eth_axis_tx.v | 15,017 | module MODULE1 #
(
parameter VAR13 = 8,
parameter VAR17 = (VAR13>8),
parameter VAR15 = (VAR13/8)
)
(
input wire clk,
input wire rst,
input wire VAR16,
output wire VAR14,
input wire [47:0] VAR25,
input wire [47:0] VAR1,
input wire [15:0] VAR7,
input wire [VAR13-1:0] VAR6,
input wire [VAR15-1:0] VAR24,
input wire VAR20,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3/sky130_fd_sc_ls__nor3.functional.pp.v | 1,844 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR12 ,
VAR11 ,
VAR1,
VAR3,
VAR14 ,
VAR6
);
output VAR5 ;
input VAR10 ;
input VAR12 ;
input VAR11 ;
input VAR1;
input VAR3;
input VAR14 ;
input VAR6 ;
wire VAR13 ;
wire VAR8;
nor VAR4 (VAR13 , VAR11, VAR10, VAR12 );
VAR2 VAR9 (VAR8, VAR13, VAR1, VAR3);
buf VAR7 (VAR5 , VAR8 );
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/generic/ppfifo.v | 20,092 | module MODULE1
VAR3 = 4
)(
input reset,
input VAR8,
output reg [1:0] VAR30,
input [1:0] VAR43,
output [23:0] VAR22,
input VAR15,
input [VAR4 - 1: 0] VAR24,
output reg VAR37,
input VAR45,
input VAR34,
output reg VAR47,
input VAR17,
output reg [23:0] VAR6,
output [VAR4 - 1: 0] VAR16,
output VAR20
);
localparam VAR39 = (1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai.pp.symbol.v | 1,391 | module MODULE1 (
input VAR4,
input VAR7,
input VAR2 ,
input VAR9 ,
output VAR5 ,
input VAR3 ,
input VAR8,
input VAR6,
input VAR1
);
endmodule | apache-2.0 |
qeedquan/fpga | de2-115/uart_hello/uart_hello.v | 1,044 | module MODULE1
(
input wire VAR3,
input wire VAR6,
input wire VAR14,
output wire VAR4,
output wire VAR9
);
reg [8*VAR5:0] VAR11 = "VAR2 VAR10!\VAR13\VAR1";
reg [7:0] VAR7;
wire rst;
wire VAR8;
integer VAR15, VAR12; | mit |
eda-globetrotter/PicenoDecoders | zhiyang_extra_credit_2/scripts/spare/build15/decoder_pl.v | 2,630 | module MODULE1 (VAR3,VAR16);
output [6:0] VAR16;
input [11:0] VAR3;
reg [6:0] VAR16;
reg [4:0] VAR1;
reg [11:0] VAR10;
parameter VAR9 = 5'b01110;
parameter VAR5 = 5'b10000;
parameter VAR14 = 5'b01000;
parameter VAR11 = 5'b01111;
parameter VAR6 = 5'b11010;
parameter VAR12 = 5'b11011;
parameter VAR13 = 5'b00000;
paramete... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/fpu/hardlogic/bfly.v | 2,514 | module MODULE1(VAR16,
reset,
VAR15,
VAR45,
VAR27,
VAR38,
VAR24,
VAR30,
VAR36,
VAR34
);
input VAR16;
input reset;
input [VAR21-1:0] VAR15;
input [VAR21-1:0] VAR45;
input [VAR21-1:0] VAR27;
input [VAR21-1:0] VAR38;
input [VAR21-1:0] VAR24;
input [VAR21-1:0] VAR30;
output [VAR21-1:0] VAR36;
output [VAR21-1:0] VAR34;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4bb/sky130_fd_sc_hd__nand4bb.blackbox.v | 1,336 | module MODULE1 (
VAR1 ,
VAR6,
VAR9,
VAR7 ,
VAR3
);
output VAR1 ;
input VAR6;
input VAR9;
input VAR7 ;
input VAR3 ;
supply1 VAR2;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sdd1/msu_databuf.v | 9,197 | module MODULE1 (
VAR38,
VAR52,
VAR33,
VAR43,
VAR31,
VAR25);
input VAR38;
input [7:0] VAR52;
input [13:0] VAR33;
input [13:0] VAR43;
input VAR31;
output [7:0] VAR25;
tri1 VAR38;
tri0 VAR31;
wire [7:0] VAR15;
wire [7:0] VAR25 = VAR15[7:0];
VAR49 VAR50 (
.VAR9 (VAR43),
.VAR35 (VAR33),
.VAR37 (VAR38),
.VAR7 (VAR52),
.VAR11... | gpl-2.0 |
flycrow/pyxdl | logicanalyzer/serial_wb_io.v | 3,298 | module MODULE1(
VAR3, VAR5, VAR16, VAR4,
VAR19, VAR6, VAR8, VAR20,
VAR9, VAR36, VAR32, VAR24,
VAR37, VAR14, VAR2, VAR18, VAR15, VAR22, VAR31,
VAR12, VAR10, VAR7, VAR11, VAR29
);
input wire VAR37;
input wire VAR14;
input wire VAR2;
output VAR3;
input wire [7:0] VAR18;
input wire [7:0] VAR15;
output reg [7:0] VAR5;
input... | gpl-2.0 |
nyaxt/dmix | nkmd/arch/nkmd_dai.v | 3,395 | module MODULE2(
input wire clk,
input wire rst,
input wire [23:0] VAR13,
input wire VAR6,
input wire [31:0] VAR1,
output wire [31:0] VAR15,
input wire [31:0] VAR5,
input wire VAR18);
reg [5:0] VAR14;
always @(posedge clk) begin
if (rst)
VAR14 <= 0;
end
else if (VAR6)
VAR14 <= VAR14 + 1;
end
reg [23:0] VAR8 [63:0];
alwa... | mit |
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