repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/quan.v | 37,724 | module MODULE1(
clk ,
rst ,
type ,
VAR107 ,
VAR203 ,
VAR205 ,
VAR71 ,
VAR307 ,
VAR227 ,
VAR371 ,
VAR111 ,
VAR51 ,
VAR105 ,
VAR42 ,
VAR330 ,
VAR117 ,
VAR366 ,
VAR355,
VAR151,
VAR353,
VAR162,
VAR286,
VAR304,
VAR214,
VAR38,
VAR123,
VAR144,
VAR283,
VAR242,
VAR322,
VAR267,
VAR106,
VAR324,
VAR326,
VAR318,
VAR190,
VAR182,
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.pp.symbol.v | 1,273 | module MODULE1 (
input VAR2 ,
input VAR3,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold0/sky130_fd_sc_lp__bushold0_1.v | 2,184 | module MODULE1 (
VAR4 ,
VAR3,
VAR5 ,
VAR2 ,
VAR6 ,
VAR8
);
inout VAR4 ;
input VAR3;
input VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
VAR7 VAR1 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4 ,
VAR3
);
inout VAR4 ;
input VAR3;
supply1 VAR5;
supply0 VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/phy/phy_pd_top.v | 16,333 | module MODULE1 #
(
parameter VAR66 = 100, parameter VAR14 = 3, parameter VAR19 = 8, parameter VAR59 = 16, parameter VAR45 = "VAR74", parameter VAR64 = 8, parameter VAR57 = "VAR24", parameter VAR79 = "VAR6", parameter VAR60 = "VAR46" )
(
input clk,
input rst,
input VAR18, output VAR5, input VAR58, input VAR4, output reg... | lgpl-3.0 |
ucb-bar/plsi | src/addons/core-generator/counter/src/CounterHarness.v | 1,368 | module MODULE1;
reg [1023:0] VAR1 = 0;
begin
begin
begin
begin
begin
end
begin
begin
begin | bsd-3-clause |
freecores/zet86 | rtl-model/util/div_su.v | 4,959 | module MODULE1(clk, VAR4, VAR13, VAR18, VAR7, VAR19, VAR10, VAR3);
parameter VAR1 = 16;
parameter VAR20 = VAR1 /2;
input clk; input VAR4;
input [VAR1-1:0] VAR13; input [VAR20-1:0] VAR18; output [VAR20 :0] VAR7; output [VAR20 :0] VAR19; output VAR10;
output VAR3;
reg [VAR20:0] VAR7, VAR19;
reg VAR10;
reg VAR3;
reg [VAR1... | gpl-3.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/gpio.v | 1,186 | module MODULE1 (
input VAR11, input VAR5,
input VAR10,
output [15:0] VAR13,
input [15:0] VAR4,
input [ 1:0] VAR8,
input VAR2,
input VAR1,
input VAR3,
output VAR9,
output reg [7:0] VAR6, input [7:0] VAR12
);
wire VAR7;
assign VAR7 = VAR3 & VAR1;
assign VAR9 = VAR7;
assign VAR13 = VAR10 ? { 8'h00, VAR6 } : { 8'h00, VAR12... | gpl-3.0 |
titorgalaxy/Titor | rtl/verilog/util/xilinx/Memory.v | 2,704 | module MODULE1(
dout,
din,
address,
VAR21,
VAR20,
enable,
clk,
reset
);
parameter VAR10 = VAR8;
output [VAR24-1:0] dout;
input [VAR24-1:0] din;
input [VAR24-1:0] address;
input [VAR12-1:0] VAR21;
input VAR20;
input enable;
input clk;
input reset;
wire [VAR24-1:0] VAR17;
wire [VAR24-1:0] VAR1;
wire[VAR24-1:0] VAR13;
ass... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_prio_enc.v | 247,117 | module MODULE1
(VAR3, VAR2);
parameter VAR5 = 8;
parameter VAR6 = 0;
localparam VAR1 = VAR4(VAR5);
input [0:VAR5-1] VAR3;
output [0:VAR1-1] VAR2;
reg [0:VAR1-1] VAR2;
generate
if(VAR5 < 2)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin... | gpl-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_txcounters.v | 8,668 | module MODULE1 (VAR36, VAR20, VAR22, VAR38, VAR15, VAR2,
VAR31, VAR30, VAR24, VAR16, VAR28, VAR27,
VAR10, VAR1, VAR4, VAR19, VAR26, VAR9, VAR29, VAR5,
VAR11, VAR17, VAR33, VAR14, VAR32, VAR21,
VAR7, VAR18, VAR23, VAR34, VAR12, VAR8
);
parameter VAR6 = 1;
input VAR19; input VAR26; input VAR36; input VAR20; input [1:0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.symbol.v | 1,356 | module MODULE1 (
input VAR2,
output VAR4
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
efabless/openlane | designs/aes192/src/aes192.v | 26,484 | module MODULE9 (clk, state, VAR107, out);
input clk;
input [127:0] state;
input [191:0] VAR107;
output [127:0] out;
reg [127:0] VAR5;
reg [191:0] VAR93;
wire [127:0] VAR20, VAR59, VAR2, VAR103, VAR99, VAR27, VAR64, VAR18, VAR66, VAR60, VAR12;
wire [191:0] VAR79, VAR109, VAR41, VAR100, VAR25, VAR110, VAR30, VAR49, VAR92... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper.v | 19,978 | module MODULE1 (
VAR9,
VAR51,
VAR31,
VAR45,
VAR148,
VAR130,
VAR164,
VAR183,
VAR85,
VAR41,
VAR30,
VAR90,
VAR24,
VAR2,
VAR171,
VAR179,
VAR80,
VAR174,
VAR160,
VAR42,
VAR56,
VAR6,
VAR141,
VAR35,
VAR93,
VAR88,
VAR99,
VAR58,
VAR180,
VAR43,
VAR167,
VAR46,
VAR126,
VAR154,
VAR75,
VAR83,
VAR1,
VAR144,
VAR68,
VAR157,
VAR113,
VAR3... | gpl-3.0 |
ak-fau/fpga-cyclone_iv | bemicro/alt_rom.v | 6,509 | module MODULE1 (
address,
VAR54,
VAR39);
input [11:0] address;
input VAR54;
output [31:0] VAR39;
tri1 VAR54;
wire [31:0] VAR24;
wire [31:0] VAR39 = VAR24[31:0];
VAR10 VAR4 (
.VAR8 (address),
.VAR21 (VAR54),
.VAR27 (VAR24),
.VAR2 (1'b0),
.VAR23 (1'b0),
.VAR35 (1'b1),
.VAR3 (1'b0),
.VAR7 (1'b0),
.VAR22 (1'b1),
.VAR45 (1'... | bsd-2-clause |
silent-observer/RCPU | CPU/source/InterruptController.v | 2,531 | module MODULE1 (
input wire rst,
input wire clk,
input wire VAR29,
output reg irq,
input wire VAR8,
output reg[31:0] VAR16,
output reg[15:0] VAR26,
inout wire VAR27,
inout wire VAR34,
input wire[31:0] addr,
input wire VAR11,
input wire VAR36,
input wire[3:0] VAR4,
input wire VAR35,
input wire[31:0] VAR1, VAR10, VAR14, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi.blackbox.v | 1,364 | module MODULE1 (
VAR6 ,
VAR5,
VAR3,
VAR7,
VAR9
);
output VAR6 ;
input VAR5;
input VAR3;
input VAR7;
input VAR9;
supply1 VAR2;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
vvk/sysrek | skin_color_segm/closing3x3.v | 1,595 | module MODULE1#(
parameter [9:0] VAR23 = 83 )(
input clk,
input VAR4,
input rst,
input VAR5,
input VAR3,
input VAR19,
input VAR13,
output VAR14,
output VAR10,
output VAR8,
output VAR1
);
wire VAR18;
wire VAR2;
wire VAR9;
wire VAR17;
VAR16 #
(
.VAR23(VAR23)
)
VAR21
(
.clk(clk),
.VAR4(1'b1),
.rst(1'b0),
.VAR5(VAR5),
.VAR... | gpl-2.0 |
sharebrained/medusa | hdl/medusa_cape/por.v | 1,078 | module MODULE1 (
input clk,
output reg rst
);
reg [31:0] counter;
always @(posedge clk) begin
if (counter < 32'hffffff) begin
rst <= 1;
counter <= counter + 1;
end
else begin
rst <= 0;
end
end
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_4.behavioral.v | 1,180 | module MODULE1( VAR5, VAR3, VAR6 );
input VAR5, VAR3;
output VAR6;
VAR4 VAR1(.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6));
VAR4 VAR2(.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.functional.v | 1,648 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR3
);
output VAR8 ;
input VAR6 ;
input VAR3;
wire VAR5 ;
wire VAR2;
not VAR4 (VAR5 , VAR3 );
and VAR1 (VAR2, VAR3, VAR6 );
buf VAR7 (VAR8 , VAR2 );
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v | 10,945 | module MODULE1 # (
parameter
VAR35 = 3,
VAR7 = 25,
VAR54 = 32,
VAR6 = 8,
VAR46 = 4,
VAR19 = 0
)
(
VAR13, VAR60,
VAR49, VAR47,
VAR26, VAR56, VAR11, VAR5, VAR55, VAR14, VAR66, VAR65, VAR40, VAR44,
VAR45, VAR1, VAR36, VAR48,
VAR16,
VAR34,
VAR25,
VAR51,
VAR20,
VAR32,
VAR10,
VAR22,
VAR58,
VAR4,
VAR29,
VAR41,
VAR57,
VAR61,
V... | gpl-3.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_xbar_0/synth/image_processing_2d_design_xbar_0.v | 28,504 | module MODULE1 (
VAR65,
VAR128,
VAR34,
VAR131,
VAR77,
VAR29,
VAR133,
VAR102,
VAR16,
VAR10,
VAR20,
VAR4,
VAR103,
VAR120,
VAR119,
VAR106,
VAR112,
VAR104,
VAR56,
VAR19,
VAR86,
VAR88,
VAR90,
VAR89,
VAR3,
VAR26,
VAR64,
VAR61,
VAR69,
VAR31,
VAR132,
VAR43,
VAR40,
VAR18,
VAR36,
VAR74,
VAR8,
VAR127,
VAR23,
VAR95,
VAR66,
VAR22,
... | gpl-2.0 |
vvk/sysrek | skin_color_segm/rgb2ycbcr.v | 5,380 | module MODULE1(
input clk,
input VAR20,
input [7:0] VAR17,
input [7:0] VAR43,
input [7:0] VAR55,
input VAR30, input VAR14, input VAR61,
output [7:0] VAR19,
output [7:0] VAR63,
output [7:0] VAR21,
output VAR18, output VAR47, output VAR37
);
reg signed [17:0] VAR46 = 18'b001001100100010110;
reg signed [17:0] VAR62 = 18'b... | gpl-2.0 |
briburrell/amica | device/natura_salsa8/natura_salsa8.srcs/sources_1/imports/natura_salsa8/ztex_ufm1_15y1.v | 10,614 | module MODULE1 (VAR104, reset, select, VAR30, VAR119, VAR34, VAR59, VAR87, VAR76, VAR33, VAR73, read, write);
input VAR104, select, reset, VAR30, VAR119, VAR34, VAR59, VAR87, VAR76, VAR33, VAR73;
input [7:0] read;
output [7:0] write;
function integer VAR63; input integer VAR32;
begin
VAR32 = VAR32-1;
for (VAR63=0; VAR3... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/dram.v | 51,559 | module MODULE1 #
(
parameter VAR244 = 3,
parameter VAR237 = 1,
parameter VAR52 = 10,
parameter VAR124 = 1,
parameter VAR150 = 1,
parameter VAR15 = 1,
parameter VAR121 = 5,
parameter VAR3 = 6,
parameter VAR302 = 8,
parameter VAR247 = 8,
parameter VAR65 = 64,
parameter VAR223 = 8,
parameter VAR151 = 3,
parameter VAR312 =... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/host_interface/uart/uart_io_handler.v | 13,524 | module MODULE1 #(
parameter VAR25 = 115200
)(
input clk,
input rst,
output reg VAR5,
output VAR26,
input VAR59,
output reg [31:0] VAR54,
output reg [31:0] VAR23,
output reg [31:0] VAR36,
output reg [27:0] VAR18,
output reg VAR3,
input VAR50,
input [31:0] VAR8,
input [31:0] VAR24,
input [31:0] VAR43,
input [27:0] VAR37,... | mit |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/plb_tft_cntlr_ref_v1_00_c/hdl/verilog/tft_if.v | 8,914 | module MODULE1(
clk, rst, VAR55, VAR38, VAR35, VAR32, VAR26, VAR52, VAR21, VAR61, VAR2, VAR70, VAR45, VAR23, VAR17, VAR62, VAR60, VAR3, VAR44, VAR39, VAR46, VAR59, VAR31, VAR36, VAR69, VAR65, VAR28, VAR41, VAR13, VAR68, VAR40, VAR25, VAR12, VAR30, VAR5, VAR66, VAR11, VAR56, VAR47, VAR54, VAR63, VAR67, VAR51, VAR42, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3.pp.blackbox.v | 1,325 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR8 ,
VAR1 ,
VAR5,
VAR3,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
input VAR5;
input VAR3;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axis_timer_v1_0/src/axis_timer.v | 1,236 | module MODULE1 #
(
parameter integer VAR14 = 64
)
(
input wire VAR5,
input wire VAR12,
input wire VAR4,
input wire VAR9,
input wire [VAR14-1:0] VAR8,
output wire VAR2,
output wire [VAR14-1:0] VAR11,
output wire VAR6,
input wire VAR7
);
reg [VAR14-1:0] VAR10, VAR13;
wire VAR1;
always @(posedge VAR5)
begin
if(~VAR12)
beg... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9652/axi_ad9652_channel.v | 7,008 | module MODULE1 (
VAR41,
VAR77,
VAR59,
VAR22,
VAR23,
VAR32,
VAR74,
VAR81,
VAR68,
VAR54,
VAR25,
VAR3,
VAR13,
VAR27,
VAR56,
VAR36,
VAR65,
VAR33,
VAR30,
VAR47,
VAR60);
parameter VAR15 = 0;
parameter VAR67 = 0;
parameter VAR46 = 0;
input VAR41;
input VAR77;
input [15:0] VAR59;
input VAR22;
output [15:0] VAR23;
input [15:0] ... | gpl-3.0 |
azonenberg/yosys | techlibs/intel/cycloneiv/cells_map.v | 3,535 | module \VAR7 (input VAR36, VAR14, output VAR10);
parameter VAR12="VAR31";
VAR8 #(.VAR39(VAR12)) VAR43 (.VAR32(VAR36), .VAR15(VAR10), .clk(VAR14), .VAR11(1'b1), .VAR19(1'b1), .VAR42(1'b1), .VAR29(1'b0), .VAR5(1'b0), .VAR2(1'b0), .VAR4(1'b0));
endmodule
module \VAR1 (input VAR36, VAR14, output VAR10);
parameter VAR12="VA... | isc |
ShepardSiegel/ocpi | libsrc/hdl/bsv/BRAM1BE.v | 4,016 | module MODULE1(VAR14,
VAR15,
VAR11,
VAR4,
VAR17,
VAR6
);
parameter VAR8 = 0;
parameter VAR3 = 1;
parameter VAR9 = 1;
parameter VAR1 = 1;
parameter VAR7 = 1;
parameter VAR12 = 1;
input VAR14;
input VAR15;
input [VAR7-1:0] VAR11;
input [VAR3-1:0] VAR4;
input [VAR9-1:0] VAR17;
output [VAR9-1:0] VAR6;
reg [VAR9-1:0] VAR13[... | lgpl-3.0 |
marmolejo/zet | cores/zet/rtl/zet_regfile.v | 3,071 | module MODULE1 (
output [15:0] VAR20,
output [15:0] VAR29,
output [15:0] VAR26,
output [15:0] VAR16,
output [15:0] VAR19,
input [31:0] VAR15,
output [15:0] VAR12,
output reg [8:0] VAR1,
input wr,
input VAR14,
input VAR4,
input clk,
input rst,
input [ 3:0] VAR27,
input [ 3:0] VAR13,
input [ 3:0] VAR8,
input [ 3:0] VAR22... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/pipectrl.v | 2,280 | module MODULE1
parameter VAR16 = 1)
(input clk,
input reset,
input VAR13,
output VAR17,
output VAR21,
input VAR2,
output [VAR4-1:0] VAR10,
output [VAR4-1:0] VAR18,
input [VAR16-1:0] VAR8,
output [VAR16-1:0] VAR14);
wire VAR9 = VAR13 & VAR17;
wire VAR15 = VAR21 & VAR2;
wire [VAR16-1:0] VAR11 [VAR4-1:0];
assign VAR17 = ~... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b_2.v | 2,311 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR6 ,
VAR10 ,
VAR7 ,
VAR11,
VAR8,
VAR9 ,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR10 ;
input VAR7 ;
input VAR11;
input VAR8;
input VAR9 ;
input VAR5 ;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR9(VAR9),
.... | apache-2.0 |
chaohu/Daily-Learning | Verilog/lab2/lab2_3/lab3_1_2/lab3_1_2.srcs/sources_1/new/decoder_74138_dataflow.v | 1,059 | module MODULE1(
input [2:0] VAR3,
input VAR4,VAR5,VAR1,
output [7:0] VAR2
);
assign VAR2[0] = VAR5|VAR1|(~VAR4)|VAR3[0]|VAR3[1]|VAR3[2];
assign VAR2[1] = VAR5|VAR1|(~VAR4)|VAR3[0]|VAR3[1]|(~VAR3[2]);
assign VAR2[2] = VAR5|VAR1|(~VAR4)|VAR3[0]|(~VAR3[1])|VAR3[2];
assign VAR2[3] = VAR5|VAR1|(~VAR4)|VAR3[0]|(~VAR3[1])|(~V... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_2.behavioral.v | 1,108 | module MODULE1( VAR2, VAR5 );
input VAR2;
output VAR5;
VAR3 VAR4(.VAR2(VAR2),.VAR5(VAR5));
VAR3 VAR1(.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ui_cmd.v | 8,144 | module MODULE1 #
(
parameter VAR56 = 100,
parameter VAR46 = 33,
parameter VAR43 = 3,
parameter VAR54 = 12,
parameter VAR24 = 5,
parameter VAR11 = 2,
parameter VAR32 = 16,
parameter VAR47 = 4,
parameter VAR6 = "VAR30"
)
(
VAR28, VAR19, VAR12, VAR48, VAR14, VAR13, VAR55, VAR36, VAR3,
VAR16, VAR15, VAR51,
rst, clk, VAR1, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha.functional.v | 1,415 | module MODULE1 (
VAR10,
VAR3 ,
VAR6 ,
VAR1
);
output VAR10;
output VAR3 ;
input VAR6 ;
input VAR1 ;
wire VAR7;
wire VAR9 ;
and VAR4 (VAR7, VAR6, VAR1 );
buf VAR2 (VAR10 , VAR7 );
xor VAR8 (VAR9 , VAR1, VAR6 );
buf VAR5 (VAR3 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp.behavioral.v | 2,775 | module MODULE1 (
VAR27 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR18 ,
VAR29
);
output VAR27 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR18 ;
input VAR29;
supply1 VAR30;
supply0 VAR4;
supply1 VAR20 ;
supply0 VAR31 ;
wire VAR21 ;
wire VAR19 ;
wire VAR10 ;
reg VAR26 ;
wire VAR17 ;
wire VAR11 ;
wire VAR24 ;
wire VAR25;
wire VAR9 ;
w... | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_video_csc.v | 6,995 | module MODULE1 (
clk,
reset,
VAR33,
VAR35,
VAR1,
VAR5,
VAR16,
VAR26,
VAR21,
VAR25,
VAR32,
VAR14,
VAR23,
VAR24
);
parameter VAR15 = 23;
parameter VAR12 = 23;
parameter VAR13 = 1;
parameter VAR31 = 1;
input clk;
input reset;
input [VAR15: 0] VAR33;
input VAR35;
input VAR1;
input [VAR13:0] VAR5;
input VAR16;
input VAR26;
... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/wr_gray_ctr.v | 3,996 | module MODULE1( clk,
reset,
VAR10,
VAR3 );
input clk;
input reset;
input VAR10;
output [3:0] VAR3;
reg [3:0] din;
wire [3:0] VAR7;
assign VAR3 = VAR7;
always @(VAR7)
begin
case (VAR7)
4'b0000 : din <= 4'b0001; 4'b0001 : din <= 4'b0011; 4'b0010 : din <= 4'b0110; 4'b0011 : din <= 4'b0010; 4'b0100 : din <= 4'b1100; 4'b010... | lgpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemFaces/MemFaces_stub.v | 1,262 | module MODULE1(VAR1, VAR2, VAR3)
;
input VAR1;
input [9:0]VAR2;
output [799:0]VAR3;
endmodule | gpl-3.0 |
sabertazimi/hust-lab | digitalLogic/labs/lab4/src/flow_led.v | 2,976 | module MODULE1(
input VAR4,
input reset,
input [4:0] VAR24, input VAR21,
output reg [3:0] state
);
parameter VAR13 = 32;
parameter VAR18 = 0, VAR16 = 1,
VAR12 = 3,
VAR8 = 2,
VAR1 = 6,
VAR6 = 7,
VAR9 = 5,
VAR5 = 4,
VAR7 = 12,
VAR19 = 13,
VAR10 = 15,
VAR2 = 14,
VAR3 = 10,
VAR22 = 11,
VAR14 = 9,
VAR11 = 8;
reg [3:0] VAR23... | mit |
cpulabs/mist1032isa | src/core/l1_instruction/l1_inst_cache.v | 13,930 | module MODULE1(
input wire VAR4,
input wire VAR71,
input wire VAR46,
input wire VAR54,
input wire VAR14,
output wire VAR75,
input wire VAR49,
output wire [1:0] VAR63,
output wire [2:0] VAR74,
output wire [13:0] VAR6,
output wire [31:0] VAR47,
output wire [31:0] VAR72,
input wire VAR26,
output wire VAR22,
input wire [63... | bsd-2-clause |
asicguy/gplgpu | hdl/vga/sm_arb.v | 4,350 | module MODULE1
(
input VAR9,
input VAR14,
input VAR10,
input VAR3,
input VAR13,
input VAR17,
input VAR4,
input VAR16,
input VAR7,
input VAR20,
output reg VAR21,
output reg VAR6,
output reg VAR8
);
reg [2:0] VAR1;
reg [2:0] VAR15;
parameter VAR11 = 3'd0,
VAR12 = 3'd2,
VAR5 = 3'd3,
VAR18 = 3'd4,
VAR19 = 3'd5,
VAR2 = 3'd6... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPCG_Toggle_bCMD_IDLE.v | 3,881 | module MODULE1
(
parameter VAR5 = 4
)
(
VAR7 ,
VAR15 ,
VAR9 ,
VAR3 ,
VAR12 ,
VAR14 ,
VAR2 ,
VAR4 ,
VAR8 ,
VAR10 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR13
);
output VAR7 ;
output [31:0] VAR15 ;
output VAR9 ;
output VAR3 ;
output [7:0] VAR12 ;
output [2:0] VAR14 ;
output [VAR5 - 1:0] VAR2 ;
output [15:0] VAR4 ;
output VAR8 ;
output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b.behavioral.v | 1,442 | module MODULE1 (
VAR12 ,
VAR5 ,
VAR2
);
output VAR12 ;
input VAR5 ;
input VAR2;
supply1 VAR7;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR4 ;
wire VAR10 ;
wire VAR3;
not VAR11 (VAR10 , VAR2 );
or VAR6 (VAR3, VAR10, VAR5 );
buf VAR9 (VAR12 , VAR3 );
endmodule | apache-2.0 |
olajep/oh | src/emesh/hdl/emesh_mux.v | 2,133 | module MODULE1 (
VAR6, VAR5, VAR2,
VAR10, VAR16, VAR1
);
parameter VAR13 = 32;
parameter VAR7 = 2 * VAR13 + 40;
parameter VAR18 = 99;
parameter VAR19 = "VAR9";
input [VAR18-1:0] VAR10;
input [VAR18*VAR7-1:0] VAR16;
output [VAR18-1:0] VAR6;
output VAR5;
output [VAR7-1:0] VAR2;
input VAR1;
wire [VAR18-1:0] VAR11;
reg [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.pp.symbol.v | 1,324 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_mm_interconnect_0_avalon_st_adapter_001.v | 6,192 | module MODULE1 #(
parameter VAR3 = 34,
parameter VAR20 = 0,
parameter VAR15 = 34,
parameter VAR18 = 0,
parameter VAR5 = 0,
parameter VAR1 = 0,
parameter VAR17 = 1,
parameter VAR2 = 1,
parameter VAR21 = 0,
parameter VAR11 = 34,
parameter VAR23 = 0,
parameter VAR24 = 1,
parameter VAR10 = 0,
parameter VAR12 = 1,
parameter... | gpl-3.0 |
dachdecker2/icoboard_ws2812b_display | clock.v | 1,927 | module MODULE1 (
input clk,
input VAR1,
output [0:0] VAR5
);
parameter VAR3 = 10;
reg [0:0] VAR5;
reg [VAR4(VAR3):0] VAR7;
always @(posedge clk) begin
if (!VAR1) begin
VAR7 <= VAR3-1;
VAR5 <= 0;
end else begin
VAR7 <= VAR7 ? (VAR7-1) : VAR3-1;
VAR5 <= !VAR7;
end
end
reg [VAR4(VAR3):0] VAR2; reg [10:0] VAR6 = 0;
reg [0:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31oi/sky130_fd_sc_ms__a31oi.functional.v | 1,448 | module MODULE1 (
VAR4 ,
VAR7,
VAR5,
VAR8,
VAR2
);
output VAR4 ;
input VAR7;
input VAR5;
input VAR8;
input VAR2;
wire VAR3 ;
wire VAR1;
and VAR9 (VAR3 , VAR8, VAR7, VAR5 );
nor VAR6 (VAR1, VAR2, VAR3 );
buf VAR10 (VAR4 , VAR1 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_iodll/rtl/bw_iodll.v | 1,748 | module MODULE1(
VAR11,
VAR4,
VAR6,
VAR3,
VAR5,
VAR13,
VAR8,
VAR12,
VAR1,
VAR9,
VAR7,
VAR10,
VAR2
);
input [4:0] VAR11;
input VAR4;
input VAR6;
input [2:0] VAR3;
input VAR5;
input VAR13;
input VAR8;
input VAR12;
output VAR1;
output [4:0] VAR9;
output VAR7;
output VAR10;
output VAR2;
assign VAR9 = (VAR5 == 1'b0)? VAR11:5... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.functional.pp.v | 1,611 | module MODULE1( VAR16, VAR19, VAR11, VAR5, VAR21, VAR7 );
input VAR19, VAR16, VAR11;
inout VAR21, VAR7;
output VAR5;
wire VAR9;
not VAR15( VAR9, VAR11 );
wire VAR13;
and VAR2( VAR13, VAR9, VAR19, VAR16 );
wire VAR14;
not VAR12( VAR14, VAR16 );
wire VAR18;
and VAR8( VAR18, VAR14, VAR19, VAR11 );
wire VAR1;
not VAR3( VAR... | apache-2.0 |
asicguy/gplgpu | hdl/de_temp/der_misc.v | 4,332 | module MODULE1
(
input VAR9,
input VAR14,
input VAR20,
input VAR10,
input [1:0] VAR13, input VAR3,
input [31:0] VAR1,
input [31:0] VAR7,
input [1:0] VAR2,
input VAR4,
output reg VAR5,
output VAR18,
output VAR17,
output VAR6,
output VAR12,
output [31:0] VAR16,
output [31:0] VAR11,
output [27:0] VAR19,
output [27:0] VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b.behavioral.pp.v | 1,998 | module MODULE1 (
VAR14 ,
VAR3 ,
VAR8 ,
VAR10 ,
VAR16 ,
VAR6,
VAR13,
VAR7 ,
VAR9
);
output VAR14 ;
input VAR3 ;
input VAR8 ;
input VAR10 ;
input VAR16 ;
input VAR6;
input VAR13;
input VAR7 ;
input VAR9 ;
wire VAR11 ;
wire VAR12 ;
wire VAR2;
not VAR17 (VAR11 , VAR16 );
or VAR4 (VAR12 , VAR11, VAR10, VAR8, VAR3 );
VAR15 V... | apache-2.0 |
ruishihan/R7-with-notes | src/rtl/A2S_controller.v | 2,979 | module MODULE1(
rst,
VAR13,
sync,
VAR8,
VAR27,
VAR19,
VAR10,
VAR9,
VAR1,
VAR16,
VAR3,
VAR17,
VAR21,
VAR28,
VAR15,
VAR24,
VAR5,
VAR7,
VAR23
);
parameter VAR6 = 3'd0;
parameter VAR12 = 3'd1;
parameter VAR25 = 3'd2;
parameter VAR14 = 3'd3;
input rst,VAR13,sync,VAR8;
output[4:0] VAR27;
input VAR16;
input VAR3;
output reg[3... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_prbs_gen.v | 7,545 | module MODULE1 #
(
parameter VAR4 = 100, parameter VAR3 = 64 )
(
input VAR1, input VAR9, input VAR15, input [VAR3-1:0] VAR8, input VAR14, input VAR16, output [VAR3-1:0] VAR18 );
function integer VAR17 (input integer VAR10);
begin
VAR10 = VAR10 - 1;
for (VAR17=1; VAR10>1; VAR17=VAR17+1)
VAR10 = VAR10 >> 1;
end
endfuncti... | mit |
kylemsguy/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-B/pbkdfengine.v | 19,877 | module MODULE1
(VAR12, VAR40, VAR45, VAR80, VAR53, VAR100, VAR70, VAR16, VAR75, VAR2, VAR51,
VAR91, VAR47, VAR33, VAR106, VAR99, VAR73, VAR96);
input VAR12; input VAR40;
input [255:0] VAR45;
input [255:0] VAR80;
input [127:0] VAR53;
input [31:0] VAR100;
input [3:0] VAR70;
output [31:0] VAR16;
output [31:0] VAR75;
outpu... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_reset.v | 3,958 | module MODULE1(
VAR3,
VAR23,
VAR10,
VAR6,
VAR9,
VAR8,
VAR15,
VAR35,
VAR18,
VAR14,
VAR32,
VAR40,
VAR12,
VAR41,
VAR22,
VAR33,
VAR1,
VAR4,
VAR29,
VAR31,
VAR25
);
parameter VAR19 = "";
parameter VAR17 = 1;
input VAR3;
input VAR23;
input VAR10;
input VAR6;
input VAR9;
input VAR8;
input VAR15;
output VAR35;
output VAR18;
inp... | lgpl-3.0 |
cpulabs/mist1032sa | src/core/scheduler2/regist_rbuffer_select.v | 2,438 | module MODULE1(
input wire VAR17,
input wire VAR20,
input wire VAR2,
input wire VAR32,
input wire VAR10,
input wire VAR23,
input wire VAR13,
input wire VAR6,
input wire VAR28,
input wire VAR24,
input wire VAR29,
input wire VAR33,
input wire VAR18,
input wire VAR8,
input wire VAR21,
input wire VAR22,
input wire VAR27,
i... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31o/sky130_fd_sc_ls__a31o_2.v | 2,337 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR4 ,
VAR2 ,
VAR5 ,
VAR10,
VAR7,
VAR9 ,
VAR11
);
output VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR10;
input VAR7;
input VAR9 ;
input VAR11 ;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR9(VAR9),
.VA... | apache-2.0 |
DreamIP/GPStudio | support/io/d5m/hdl/I2C_CCD_Config.v | 8,864 | module MODULE1 ( VAR16,
VAR11,
VAR8,
VAR43,
VAR18,
VAR47,
VAR5,
VAR3
);
input VAR16;
input VAR11;
input VAR8;
input VAR43;
output VAR5;
inout VAR3;
reg [15:0] VAR42;
reg [31:0] VAR41;
reg VAR27;
reg VAR24;
wire VAR35;
wire VAR29;
reg [23:0] VAR28;
reg [5:0] VAR31;
reg [3:0] VAR33;
input VAR18;
input VAR47;
parameter VA... | gpl-3.0 |
Kumikomi/openreroc_posturesensor | hardware/src/sensor_ctl.v | 4,270 | module MODULE1(
input [0:0] clk,
input VAR43,
input [31:0] VAR10,
input [0:0] VAR30,
input [0:0] VAR23,
output [31:0] VAR15,
output [0:0] VAR58,
output [0:0] VAR26,
input [0:0] VAR11,
output [0:0] VAR47,
output [0:0] VAR55,
output [0:0] VAR53,
input [0:0] VAR14,
output [0:0] VAR21,
output [0:0] VAR40,
output [0:0] VAR4... | bsd-3-clause |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/credit_producer.v | 4,362 | module MODULE1 (
clk,
VAR13,
VAR11,
VAR6,
VAR7,
VAR10,
VAR4
);
parameter VAR14 = 1;
parameter VAR3 = 1;
parameter VAR9 = 1;
parameter VAR16 = 1;
parameter VAR12 = 1;
input clk;
input VAR13;
input VAR11;
input VAR6;
input VAR7;
output reg [15 : 0] VAR10;
output reg [15 : 0] VAR4;
reg VAR1;
reg VAR15;
reg [15 : 0] VAR2;
... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v | 4,013 | module MODULE4
(
inout [35:0] VAR9,
inout [35:0] VAR4,
inout [35:0] VAR8,
inout [35:0] VAR7,
inout [35:0] VAR5
) ;
endmodule
module MODULE1
(
input VAR6,
input [383:0] VAR11,
input [7:0] VAR3,
inout [35:0] VAR1
) ;
endmodule
module MODULE2
(
input [255:0] VAR10,
inout [35:0] VAR1
) ;
endmodule
module MODULE3
(
output [... | lgpl-3.0 |
jobisoft/jTDC | modules/datapipe.v | 2,473 | module MODULE1 (VAR5,
VAR10,
VAR7);
parameter VAR2 = 32;
parameter VAR8 = 0;
parameter VAR1 = "VAR4";
input wire VAR5;
input wire [VAR2-1:0] VAR10;
output wire [VAR2-1:0] VAR7;
genvar VAR9;
generate
if (VAR8>0) begin
reg [VAR2-1:0] VAR6 [VAR8-1:0];
always@(posedge VAR5) begin
VAR6[0] <= VAR10;
end
for (VAR9=1;VAR9<VAR8... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb.pp.symbol.v | 1,328 | module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR3 ,
input VAR2 ,
output VAR4 ,
input VAR9 ,
input VAR6,
input VAR1,
input VAR8
);
endmodule | apache-2.0 |
jameshegarty/rigel | platform/camera2.0/vsrc/CamSetup.v | 6,752 | module MODULE1 (
input clk, input VAR8,
input [16:0] VAR37, input VAR25,
output reg VAR44,
output [31:0] VAR3,
output [16:0] VAR40,
output reg VAR16,
output VAR18, inout VAR50 );
parameter VAR5 = 100000000; parameter VAR45 = 8'h42;
localparam VAR13 = 100000; localparam VAR19 = 300;
localparam integer VAR12 = (VAR5/1000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp_2.v | 2,334 | module MODULE2 (
VAR1,
VAR6 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR8
);
input VAR1;
input VAR6 ;
input VAR9 ;
output VAR5 ;
output VAR7 ;
input VAR4 ;
input VAR8 ;
VAR3 VAR2 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1,
VAR6 ,
VAR9 ,
VAR5 ,
VAR... | apache-2.0 |
Jam-G/MIPS | HAZARD.v | 1,490 | module MODULE1(
input [4:0] VAR5,VAR7,VAR11,
input VAR12,
input VAR13,
input VAR16,
input VAR17,
output reg[1:0] VAR3,
output reg VAR10,VAR15,
output reg VAR2,VAR9,
output reg VAR4,VAR14,
output reg VAR1,VAR6,
output reg VAR8
);
always @(*)
begin
if(VAR13 == 1)begin
VAR3 = 2'b01; VAR9 = 1; VAR2 = 0; VAR15 = 0;
VAR10 = ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21o/sky130_fd_sc_hs__a21o.functional.pp.v | 1,922 | module MODULE1 (
VAR5,
VAR1,
VAR12 ,
VAR8 ,
VAR3 ,
VAR4
);
input VAR5;
input VAR1;
output VAR12 ;
input VAR8 ;
input VAR3 ;
input VAR4 ;
wire VAR6 ;
wire VAR7 ;
wire VAR13;
and VAR11 (VAR6 , VAR8, VAR3 );
or VAR2 (VAR7 , VAR6, VAR4 );
VAR9 VAR14 (VAR13, VAR7, VAR5, VAR1);
buf VAR10 (VAR12 , VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o_4.v | 2,426 | module MODULE2 (
VAR6 ,
VAR12 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR9,
VAR11,
VAR8 ,
VAR3
);
output VAR6 ;
input VAR12 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR9;
input VAR11;
input VAR8 ;
input VAR3 ;
VAR10 VAR7 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/endcap/gf180mcu_fd_sc_mcu7t5v0__endcap.behavioral.pp.v | 1,069 | module MODULE1( VAR2, VAR3 );
inout VAR2, VAR3;
VAR5 VAR1(.VAR2(VAR2),.VAR3(VAR3));
VAR5 VAR4(.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o.blackbox.v | 1,395 | module MODULE1 (
VAR1 ,
VAR7,
VAR5,
VAR3,
VAR2,
VAR10
);
output VAR1 ;
input VAR7;
input VAR5;
input VAR3;
input VAR2;
input VAR10;
supply1 VAR6;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_ocm_mem.v | 7,083 | module MODULE1();
parameter VAR14 = 32'h40000; parameter VAR21 = VAR25(VAR14/VAR43);
reg [VAR11-1:0] VAR4 [0:(VAR14/VAR43)-1];
task automatic VAR29;
input [(VAR12*8)-1:0] VAR1;
input [VAR37-1:0] VAR41;
input [VAR39-1:0] VAR24;
endtask
task automatic VAR20;
input [1:0] VAR7;
input [VAR37-1:0] VAR41;
input [VAR39-1:0] VA... | gpl-3.0 |
ElegantLin/My-CPU | Snake/Snake.srcs/sources_1/new/Seg_Display.v | 4,009 | module MODULE1
(
input clk,
input rst,
input VAR5,
inout [1:0]VAR7,
output reg[15:0]VAR4,
output reg[7:0]VAR2,
output reg[3:0]sel
);
localparam VAR3 = 2'b00;
reg[31:0]VAR6;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
VAR2 <= 0;
VAR6 <= 0;
sel <= 0;
end
else if (VAR7 == VAR3) begin
VAR2 <= 0;
VAR6 <= 0;
sel... | gpl-3.0 |
osecpu/fpga | mmu.v | 1,377 | module MODULE1(clk,
VAR1, VAR14, VAR6, addr, VAR16,
VAR15, VAR13, VAR7, VAR2, VAR4);
input clk;
input [5:0] VAR1;
input [15:0] VAR14;
input [11:0] VAR6;
output [15:0] addr;
output VAR16;
input [11:0] VAR15;
input [5:0] VAR13;
input [15:0] VAR7;
input [15:0] VAR2;
input VAR4;
wire [15:0] VAR3;
wire [15:0] VAR10;
wire [5... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_17.v | 15,199 | module MODULE3 (
clk,
reset,
VAR25,
VAR7,
VAR111,
VAR13,
VAR29
);
parameter VAR20 = 18;
parameter VAR39 = 17;
parameter VAR93 = 9;
localparam VAR97 = 23;
input clk;
input reset;
input VAR25;
input VAR7;
input [VAR20-1:0] VAR111; output VAR13;
output [VAR20-1:0] VAR29;
localparam VAR36 = 18; localparam VAR76 = 36; local... | mit |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | src/fpgaminer_top.v | 5,027 | module MODULE1 (VAR31);
parameter VAR34 = VAR7;
parameter VAR34 = 0;
localparam [5:0] VAR39 = (6'd1 << VAR34);
localparam [31:0] VAR33 = (32'd1 << (7 - VAR34)) + 32'd1;
input VAR31;
reg [255:0] state = 0;
reg [511:0] VAR12 = 0;
reg [31:0] VAR37 = 32'h00000000;
wire VAR5;
VAR40 VAR17 (VAR31, VAR5);
assign VAR5 = VAR31;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_ps/sky130_fd_sc_lp__udp_dff_ps.symbol.v | 1,311 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdaptevaLib/src/i2c/hdl/parallella_i2c.v | 2,504 | module MODULE1
(
VAR18, VAR17,
VAR3, VAR23,
VAR12, VAR21, VAR13, VAR22
);
input VAR12;
input VAR21;
output VAR18;
input VAR13;
input VAR22;
output VAR17;
inout VAR3;
inout VAR23;
wire VAR3 = VAR21 ? 1'VAR4 : VAR12;
wire VAR18 = VAR3;
wire VAR23 = VAR22 ? 1'VAR4 : VAR13;
wire VAR17 = VAR23;
VAR5 #(
.VAR11(8), .VAR6("VAR... | lgpl-3.0 |
peteasa/parallella-fpga | ohLocal/dut_mands_axi_elink.v | 42,647 | module MODULE1(
VAR301, VAR136, VAR232, VAR259, VAR72,
VAR107, VAR172, VAR14, VAR207, VAR210, VAR262, VAR26, VAR269
);
parameter VAR174 = 32;
parameter VAR57 = 12'h810;
parameter VAR278 = 12;
parameter VAR227 = 12;
parameter VAR42 = 6;
parameter VAR46 = 6;
parameter VAR228 = 2*VAR174 + 40;
parameter VAR61 = 1;
paramete... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.behavioral.v | 1,098 | module MODULE1( VAR5, VAR2 );
input VAR5;
output VAR2;
VAR1 VAR4(.VAR5(VAR5),.VAR2(VAR2));
VAR1 VAR3(.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/verilog/aesl_mux_load_5_3_x_s.v | 12,668 | module MODULE1 (
VAR14,
VAR90,
VAR32,
VAR87,
VAR43,
VAR6,
VAR7,
VAR78,
VAR58,
VAR53,
VAR38,
VAR71,
VAR33,
VAR8,
VAR12,
VAR66,
VAR89,
VAR22,
VAR74,
VAR31,
VAR52,
VAR39,
VAR56,
VAR15,
VAR16,
VAR83,
VAR30,
VAR36,
VAR9,
VAR11,
VAR3,
VAR76,
VAR61,
VAR60,
VAR48,
VAR84,
VAR88
);
parameter VAR40 = 1'd1;
input VAR14;
input VAR9... | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_top.v | 14,203 | module MODULE1 (
VAR39,
VAR117,
VAR140,
VAR108,
VAR78,
VAR82,
VAR56,
VAR43,
VAR160,
VAR115,
VAR88,
VAR48,
VAR152,
VAR162,
VAR183,
VAR143,
VAR72,
interrupt,
VAR83,
VAR176,
VAR178,
VAR87,
VAR159,
VAR137,
VAR127,
VAR24,
VAR2,
VAR147,
VAR161,
VAR168,
VAR28,
VAR8,
VAR106,
VAR144,
VAR17,
VAR119,
VAR93,
VAR139
);
parameter VA... | gpl-2.0 |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/trig_cfg_fifo.v | 13,896 | module MODULE1(
VAR405,
VAR169,
VAR103,
VAR194,
din,
VAR195,
VAR29,
dout,
VAR374,
VAR385
);
input VAR405;
input VAR169;
input VAR103;
input VAR194;
input [17 : 0] din;
input VAR195;
input VAR29;
output [17 : 0] dout;
output VAR374;
output VAR385;
VAR7 #(
.VAR279(0),
.VAR239(0),
.VAR162(0),
.VAR303(0),
.VAR299(0),
.VAR1... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_pad_txrx_zctl.v | 2,062 | module MODULE1(
out,
VAR2,
VAR5, VAR9, VAR7, VAR6, VAR3, VAR4, VAR8
);
input [7:0] VAR5; input VAR8; input VAR9; input [8:1] VAR7; input [8:1] VAR6; input VAR3; input VAR4; inout VAR2;
output out;
assign VAR2 = VAR4 ? VAR3 : 1'VAR1;
assign out = VAR2;
endmodule | gpl-2.0 |
Koheron/zynq-sdk | boards/alpha250/cores/ad7124_v1_0/ad7124.v | 1,524 | module MODULE1 #()
(
input wire clk,
input wire VAR6,
input wire VAR8,
output reg VAR2,
output reg VAR4,
output reg VAR1,
output reg [24-1:0] dout,
output reg valid
);
reg [14-1:0] VAR5;
reg [24-1:0] VAR7;
VAR9 VAR5 = 0;
VAR9 VAR4 = 1;
VAR9 VAR2 = 1;
VAR9 dout = 0;
VAR9 VAR7 = 0;
localparam [8-1:0] VAR3 = 8'b01000010;
... | mit |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_audio_in_dma.v | 17,719 | module MODULE1 (
output wire [25:0] VAR3, output wire VAR58, output wire [3:0] VAR99, output wire [31:0] VAR4, input wire VAR79, input wire VAR43, input wire VAR97, input wire [31:0] VAR50, input wire VAR78, input wire [3:0] VAR84, output wire [31:0] VAR105, input wire VAR72, input wire [2:0] VAR36, input wire VAR83, o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv_6.v | 2,011 | module MODULE2 (
VAR8 ,
VAR1 ,
VAR4,
VAR3,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR1 ;
input VAR4;
input VAR3;
input VAR7 ;
input VAR6 ;
VAR5 VAR2 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8,
VAR1
);
output VAR8;
input VAR1;
supply1 VAR4;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o_4.v | 2,264 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR7,
VAR2,
VAR4 ,
VAR8
);
output VAR1 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR7;
input VAR2;
input VAR4 ;
input VAR8 ;
VAR5 VAR9 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/ps2/rtl/ps2.v | 5,442 | module MODULE1 #(
parameter VAR19 = 4'h0,
parameter VAR41 = 100000000
) (
input VAR37,
input VAR2,
input [13:0] VAR14,
input VAR13,
input [31:0] VAR30,
output reg [31:0] VAR27,
inout VAR12,
inout VAR17,
output reg irq
);
wire VAR43 = VAR14[13:10] == VAR19;
reg VAR4;
reg [9:0] VAR22;
wire enable;
assign enable = (VAR22 ... | lgpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/ramb_8_to_n.v | 3,207 | module MODULE1 (VAR15,
VAR27,
VAR33,
VAR17,
VAR11,
VAR21,
VAR4,
VAR5,
VAR22,
VAR12);
parameter VAR13 = 1024;
parameter VAR23 = 8;
localparam VAR30 = 8;
localparam VAR9 = VAR13;
localparam VAR1 = VAR24(VAR9);
localparam VAR18 = VAR23;
localparam VAR29 = VAR9*8/VAR18;
localparam VAR2 = VAR24(VAR29);
input wire VAR15;
inp... | bsd-3-clause |
khldragon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RESOURCE_SHARING_CONTROL.v | 4,860 | module MODULE1 (
input VAR9,
input VAR26,
input VAR25,
output [3:0] VAR14,
output reg VAR16,
output VAR2
);
wire [6:0] VAR19;
reg VAR17;
reg VAR18;
reg VAR20;
reg [2:0] VAR4;
reg [2:0] VAR15;
parameter VAR13 = 3'b000;
parameter VAR23 = 3'b001;
parameter VAR12 = 3'b010;
parameter VAR24 = 3'b011;
parameter VAR5 = 3'b100;... | bsd-2-clause |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_audio_0.v | 7,532 | module MODULE1 (
clk,
reset,
address,
VAR13,
read,
write,
VAR19,
VAR20,
VAR1,
irq,
VAR32,
VAR17
);
input clk;
input reset;
input [ 1: 0] address;
input VAR13;
input read;
input write;
input [31: 0] VAR19;
input VAR20;
input VAR1;
output reg irq;
output reg [31: 0] VAR32;
output VAR17;
localparam VAR31 = 15;
localparam ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.symbol.v | 1,405 | module MODULE1 (
input VAR2 ,
input VAR4 ,
input VAR8,
output VAR7
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/6-pipe_registers/latch_MEM_WB.v | 2,101 | module MODULE1
parameter VAR12=32, VAR2=5
)
(
input wire clk,
input wire reset,
input wire VAR16,
input wire [VAR12-1:0] VAR6,
input wire [VAR12-1:0] VAR9,
input wire [VAR2-1:0] VAR11,
output wire [VAR12-1:0] VAR5,
output wire [VAR12-1:0] VAR15,
output wire [VAR2-1:0] VAR13,
input wire VAR17,
input wire VAR14,
output w... | gpl-3.0 |
bluespec/Flute | builds/RV32ACIMU_Flute_iverilog/Verilog_RTL/mkUART.v | 132,390 | module MODULE1(VAR224,
VAR142,
VAR227,
VAR187,
VAR163,
VAR230,
VAR244,
VAR152,
VAR147,
VAR184,
VAR60,
VAR81,
VAR82,
VAR309,
VAR155,
VAR162,
VAR335,
VAR316,
VAR211,
VAR218,
VAR356,
VAR280,
VAR41,
VAR247,
VAR361,
VAR15,
VAR292,
VAR329,
VAR282,
VAR120,
VAR123,
VAR130,
VAR193,
VAR253,
VAR186,
VAR334,
VAR233,
VAR10,
VAR124,... | apache-2.0 |
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